ArashAhmadian

Supporting rr_graphs with non-identical horizontal and vertical channels in the Serializer

1

#### Context #1883 enables the rr_graph to model different horizontal and vertical channels. As a follow up to this feature, the seralizer should also able to support rr_graphs generated after...

ifdef-endif seems to not be recongized properly by Odin. The adder circuits located [here](https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog) are syntactically correct however Odin marks the output `sum` as undriven. #### Expected Behaviour Should synthesize...