Angelo Jacobo

Hi @ztachip , based on the error: `Free up VREF sites or create an appropriate INTERNAL_VREF constraint.` Maybe the internal VREF constraint is missing on the constraint file, I tried...

Nice to hear that. Looking on the constraint output of MIG for cs_n: ``` set_property SLEW FAST [get_ports {ddr3_cs_n[0]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}] set_property PACKAGE_PIN U8 [get_ports {ddr3_cs_n[0]}] ```...

Hi @ztachip , yes this should be correct. I'm sorry, it seems this is a problem on my controller, I forgot to turn off `ECC_TEST` which I used to test...

Hi @ztachip , @regymm is the one with the Nexys Video, he was the one who was able to make UberDDR3 work on that board. I also don't have Nexys...

Hi @debbie0-0v1, sorry for late response. Would it be possible to send here the Vivado project? Or send me via email ([email protected]). Please also let me know the Vivado version...