Missing tb.sv

[thomasnormal]

The line https://github.com/AngeloJacobo/UberDDR3/blob/main/testbench/readme.txt#L43C1-L43C5 mentions a testbench for the ddr3 module, but it doesn't appear in the repository?

[AngeloJacobo]

Hi @thomasnormal, the main testbench for the UberDDR3 simulation is this: https://github.com/AngeloJacobo/UberDDR3/blob/main/testbench/ddr3_dimm_micron_sim.sv

You can dump the whole testbench/ directory to Vivado and let it infer the hierarchy. You can follow the steps on this blog post: https://www.openiphub.com/post/getting-started-with-uberddr3-part-1-post-2#viewer-dd5kd8152