AngeloJacobo
ddr3_dimm_micron_sim.ddr3_module.U1R0.open_bank_file: at time 0 ERROR: failed to open /tmp/ddr3_dimm_micron_sim.ddr3_module.U1R0.open_bank_file.0.
OS: windows 11
Simulator version: Vivado 2024.2
Step to reproduce:
- git clone to D drive
- Run Vivado 2024.2 Tcl Shell
- Run the following command: create_project UberDDR3 D:/UberDDR3 -part xc7a200tsbg484-1 add_files -scan_for_includes {D:/UberDDR3/rtl/ddr3_top.v D:/UberDDR3/rtl/axi/axi_addr.v D:/UberDDR3/rtl/spd/spd_clk_wiz.v D:/UberDDR3/rtl/spd/spd_reader_top.v D:/UberDDR3/rtl/ddr3_phy.v D:/UberDDR3/rtl/axi/ddr3_top_axi.v D:/UberDDR3/rtl/axi/aximrd2wbsp.v D:/UberDDR3/rtl/axi/aximwr2wbsp.v D:/UberDDR3/rtl/spd/uart_tx.v D:/UberDDR3/rtl/axi/wbarbiter.v D:/UberDDR3/rtl/axi/axim2wbsp.v D:/UberDDR3/rtl/ddr3_controller.v D:/UberDDR3/rtl/axi/skidbuffer.v D:/UberDDR3/rtl/ecc/ecc_dec.sv D:/UberDDR3/rtl/spd/i2c_master.sv D:/UberDDR3/rtl/axi/sfifo.v D:/UberDDR3/rtl/ecc/ecc_enc.sv D:/UberDDR3/rtl/spd/spd_reader.v} update_compile_order -fileset sources_1 set_property SOURCE_SET sources_1 [get_filesets sim_1] add_files -fileset sim_1 -scan_for_includes {D:/UberDDR3/testbench/ddr3_dimm_micron_sim.sv D:/UberDDR3/testbench/spd_tb/i2c_slave.v D:/UberDDR3/testbench/axi_tb/ddr3_axi_traffic_gen_tb.sv D:/UberDDR3/testbench/sim_defines.vh D:/UberDDR3/testbench/ddr3.sv D:/UberDDR3/testbench/ddr3_dimm.sv D:/UberDDR3/testbench/xsim/glbl.v D:/UberDDR3/testbench/8192Mb_ddr3_parameters.vh D:/UberDDR3/testbench/ddr3_module.sv D:/UberDDR3/testbench/spd_tb/spd_reader_tb.sv} update_compile_order -fileset sim_1 update_compile_order -fileset sim_1 set_property top ddr3_dimm_micron_sim [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] update_compile_order -fileset sim_1 launch_simulation
Simulation Output: CONTROLLER PARAMETERS: ----------------------------- CONTROLLER_CLK_PERIOD = 12000 DDR3_CLK_PERIOD = 3000 ROW_BITS = 16 COL_BITS = 10 BA_BITS = 3 BYTE_LANES = 8 AUX_WIDTH = 16 MICRON_SIM = 1 ODELAY_SUPPORTED = 1 SECOND_WISHBONE = 0 WB2_ADDR_BITS = 7 WB2_DATA_BITS = 32 ECC_ENABLE = 0 ECC_INFORMATION_BITS = 57 WB_ERROR = 1
CONTROLLER LOCALPARAMS: ----------------------------- wb_addr_bits = 26 wb_data_bits = 512 wb_sel_bits = 64 wb2_sel_bits = 4 DQ_BITS = 8 row_bank_col = 1
COMMAND SLOTS: ----------------------------- READ_SLOT = 3 WRITE_SLOT = 3 ACTIVATE_SLOT = 2 PRECHARGE_SLOT = 0 REMAINING_SLOT = 1
DELAYS: ----------------------------- CL = 5 CWL = 5 PRECHARGE_TO_ACTIVATE_DELAY = 0 ACTIVATE_TO_WRITE_DELAY = 0 ACTIVATE_TO_READ_DELAY = 0 ACTIVATE_TO_PRECHARGE_DELAY = 3 ACTIVATE_TO_ACTIVATE_DELAY = 0 READ_TO_WRITE_DELAY = 1 READ_TO_READ_DELAY = 0 READ_TO_PRECHARGE_DELAY = 1 WRITE_TO_WRITE_DELAY = 0 WRITE_TO_READ_DELAY = 3 WRITE_TO_PRECHARGE_DELAY = 4 STAGE2_DATA_DEPTH = 2 READ_ACK_PIPE_WIDTH = 6
DDR3 TOP PARAMETERS: ----------------------------- CONTROLLER_CLK_PERIOD = 12000 DDR3_CLK_PERIOD = 3000 ROW_BITS = 16 COL_BITS = 10 BA_BITS = 3 BYTE_LANES = 8 AUX_WIDTH = 16 WB2_ADDR_BITS = 7 WB2_DATA_BITS = 32 MICRON_SIM = 1 ODELAY_SUPPORTED = 1 SECOND_WISHBONE = 0 WB_ERROR = 1 BIST_MODE = 1 ECC_ENABLE = 0 DIC = 0 RTT_NOM = 3 DUAL_RANK_DIMM = 0 End of DDR3 TOP PARAMETERS ----------------------------- ddr3_dimm_micron_sim.ddr3_module.U1R0.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp. WARNING: file /tmp/ddr3_dimm_micron_sim.ddr3_module.U1R0.open_bank_file.0 could not be opened ddr3_dimm_micron_sim.ddr3_module.U1R0.open_bank_file: at time 0 ERROR: failed to open /tmp/ddr3_dimm_micron_sim.ddr3_module.U1R0.open_bank_file.0. $finish called at time : 0 fs : File "D:/UberDDR3/testbench/ddr3.sv" Line 650 INFO: [USF-XSim-96] XSim completed. Design snapshot 'ddr3_dimm_micron_sim_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1267.336 ; gain = 0.000
Possible Solution: A documentation on how to create this file. Or if this file is unnecessary, delete all the related functions and function calls. etc.
Hi @kjhhgt76 , please try my suggestion on this comment: https://www.openiphub.com/post/getting-started-with-uberddr3-part-1-post-2?commentId=618a8802-c0d0-434a-81aa-735e6d42d221#viewer-oommd1130083
If it works, please let me know so I can add this instruction on this repo.
Hi @AngeloJacobo , it is working for me on vivado 2025.1 window 10, thanks
