AngeloJacobo
Build error with openxc7
Hello. I'm trying to get this working on Sechzig MX2, but I get the following error when building:
prjxray.fasm_assembler.FasmLookupError: Segment DB CFG_CENTER_MID, key CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_9.CFG_CENTER_DCIRESET_LOCKED not found from line 'CFG_CENTER_MID_X46Y32.CFG_CENTER_LOGIC_OUTS_B21_9.CFG_CENTER_DCIRESET_LOCKED' Segment DB LIOI3_TBYTESRC, key LIOI3_TBYTESRC.IOI_OCLKM_0.IOI_IMUX31_1 not found from line 'LIOI3_TBYTESRC_X0Y93.IOI_OCLKM_0.IOI_IMUX31_1' Segment DB LIOI3_TBYTESRC, key LIOI3_TBYTESRC.IOI_OCLKM_0.IOI_IMUX31_1 not found from line 'LIOI3_TBYTESRC_X0Y81.IOI_OCLKM_0.IOI_IMUX31_1' Segment DB CFG_CENTER_MID, key CFG_CENTER_MID.CFG_CENTER_DCIRESET_RST.CFG_CENTER_IMUX35_8 not found from line 'CFG_CENTER_MID_X46Y32.CFG_CENTER_DCIRESET_RST.CFG_CENTER_IMUX35_8'
It could be that I have the wrong version of openxc7. Do you have any ideas?
My code is here:
https://github.com/machdyne/UberDDR3/tree/main/example_demo/sechzig_mx2
For the OpenXC7 version I'm using (the regymm/openxc7 dockerized version), two Python scripts are required for manually placing two IOSERDES instances per each lane. As in this example: https://github.com/AngeloJacobo/UberDDR3/tree/main/example_demo/nexys_video The show_bels.py and constraints.py are called in the Makefile, manually placing the two instances (the location can be any empty differential IO pad. Vivado can place them automatically). I can help with this if it's needed.
Maybe the new version of OpenXC7 already solved it. Can I ask what version are @AngeloJacobo using for UberDDR3, and does it work on your boards without the two Python scripts?
Thanks @regymm I've added the manual constraints using the scripts from example_demo/nexys_video.
I'm still getting the same fasm errors and I don't understand exactly what they mean. I'm using the pre-built database from https://github.com/f4pga/prjxray-db and the part is xc7a35tftg256-2.
Please use the https://github.com/openxc7/prjxray-db instead, which contains the new features. You may also try the Dockerized version named regymm/openxc7 on Dockerhub. It also has a somewhat new version.
Thanks @regymm. Hi @machdyne, apologies for the delay on my reply. One suggestion which worked on my side now is to use the nix toolchain, I used the first method (Nix package manager). With that tool, you must be able to run and generate the bitfile for the arty s7 demo-project which uses the UberDDR3 on Arty S7-50.
It would be a good first step to run the already working demo projects to make sure the openxc7 toolchain you have on ypur system is working.
It's now building with the suggested prjxray-db. However, I'm not seeing anything happen on the UART when I press upper/lowercase keys. I will attempt to debug further when I get a chance. Thanks.
Please note that the baud rate is 9600. Can you see the UART response if Vivado is used for compilation instead of OpenXC7? The debug outputs are connected to LEDs (at least in the nexys video demo), and can show how far the initialization (state_calibrate in ddr3_controller.v) goes.
Hi @machdyne, I created a new demo project folder "sechzig_mx2": https://github.com/AngeloJacobo/UberDDR3/tree/main/example_demo/sechzig_mx2
I copied the files from your UberDDR3 fork.
I modified some few things like:
- No python scripts anymore
- Use another UART module
- Modify Makefile to be more compatible with OpenXC7 run (adapted from openxc7 demo-projects repo)
I also prepared two bitfiles which you can test right away on your board, one from the Vivado-generated bitfile and one from OpenXC7 run.
Let me know if any of them works on your board. The LED should light up after ~2 seconds.
Hi @machdyne , please let me know if the example demo for sechzig_mx2 works on your end so we can close this issue.
Thank you!
Sorry for the delay, I haven't been able to get this working yet but still plan to make further attempts.