Andrew Nolte

I added it to the iteration test case, but ideally it would test on all of the designs, with multiple arrays in the path. Also, while looking at the iteration...

I'm seeing it on the latest verilator, will test on xcelium as well. @marlonjames recently made some verilator vpi updates that affected this, but I think they were all just...

I understand there's going to be considerable code changes, it just doesn't seem worth it to take this out

I think slang is best positioned to be the best option for analyzing verilog because of speed and compliance. It could also be used to analyze drivers/loads, dependency tree, etc....

Hey! I fixed this on https://marketplace.visualstudio.com/items?itemName=AndrewNolte.vscode-system-verilog, along with some other improvements

This is fixed on https://github.com/AndrewNolte/vscode-system-verilog. It'll also fill in the instantiation as you type `'Module #(`, and it support interfaces

> > This is fixed on https://github.com/AndrewNolte/vscode-system-verilog. It'll also fill in the instantiation as you type `'Module #(`, and it support interfaces > > Thanks. Can it be merged with...

I was also thinking about adding more info emitters for a design, like ast, filelist, used includes, potential defines (or a .f file with all three), instance counts, etc. I...

Thanks!

I'd like to land this before putting back up the vpi iteration fixes for verilator, the last of those PRs is almost landed: https://github.com/verilator/verilator/pull/4965