AGSaidi

Tock-Register support for compare-and-swap

13

I wanted to see if there would be any support for extending Tock-registers `InMemoryRegister` to support compare-and-swap(CAS) operations. Some in memory registers can be written by hardware with a CAS...

Support building for multiple architectures

1

Support building for other architectures using the gcc atomic builtins for architectures other than x86-64.

Use an isb as a pause instruction on arm64 platforms.

3

In other projects spinlock implementations and focused testing we've found that an isb pauses execution for about the same time as an x86 pause instruction. The yield instruction behaves as...

Implement Memcmp SIMD for arm64 NEON and SVE

9

Make sure these boxes are signed before submitting your Pull Request -- thank you. - [X] I have read the contributing guide lines at https://suricata.readthedocs.io/en/latest/devguide/codebase/contributing/contribution-process.html - [X] I have signed...

Replace the yield with an isb on Arm.

5

The yield instruction is treated as a nop on Arm processors which is very different than the x86 pause instruction that stalls execution for ~40 cycles. An ISB serializes the...

Implement Memcmp SIMD for arm64 NEON and SVE

4

Make sure these boxes are checked accordingly before submitting your Pull Request -- thank you. ## Contribution style: - [X] I have read the contributing guide lines at https://docs.suricata.io/en/latest/devguide/contributing/contribution-process.html ##...