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Hello @mp-17 ， I found another problem in ara_sequencer. If there is existing an instruction of vmv8r, whcih will write v8~v15. However, there is a vmul instruction which will read...

Hello @mp-17 ， I found another problem in ara_sequencer again. If there is existing a series of instruction which need diferent cycles, like vadd and vrem. However, vrem and vsaddu...

hello， did you have sloved this problem? Our team meet the same proble when we use ara.

Thanks~ Your answer completely solved my doubts. However, there is another problem. According to the spec of rvv1.0, "If no elements are active, no additions are performed, so the scalar...

This seems to be an issue with -0.0 data. The vfredosum instruction adds vs1[0] to each element of vs2 separately. What's more, the masked element of vs2 will be replaced...

By the way, when we conducted a Lint check on the entire ARA, we found that spyglass reported that the always_comb process block cannot exceed 2000 lines, but the decoding...

Thanks for your response. Actually, I have removed the illegal detection of floating-point instruction in the dispatcher module. However, it seems that the current FPU cannot support the execution of...

Your reply has been of great help to me, and I will try to gain a deeper understanding of ara. Thakns!@mp-17

Hello, our team is also deploying FPGA for ARA. Have you ever encountered a problem where the always block is too large in decode module and causes a comprehensive abnormal...

@Joao-Pedro-Cabral ,Hello, because our improvements have not yet obtained a better PPA, our team has no plans to open our improvement. If we get a version with a better overall...