systemc topic

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Nic30

Verilator open-source SystemVerilog simulator and lint system

verilator

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

tymonx

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

sergeykhbr

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

intel

Network on Chip Simulator

davidepatti

SystemC Reference Implementation

accellera-official

RISC-V SystemC-TLM simulator

mariusmm

A Framework for Design and Verification of Image Processing Applications using UVM

nelsoncsc

This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.

anikau31