RISC-V topic
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
lbForth
Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.
MaixPy-v1
MicroPython for K210 RISC-V, let's play with edge AI easier
rCore
Rust version of THU uCore OS. Linux compatible.
neorv32
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
rv8
RISC-V simulator for x86-64
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
diosix
A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Cores-VeeR-EH1
VeeR EH1 core