ghdl topic

cryptography ip-cores in vhdl / verilog

tmeissner

Trying to verify Verilog/VHDL designs with formal methods and tools

tmeissner

Library of reusable VHDL components

tmeissner

A Python package to use FPGA development tools programmatically.

PyFPGA

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

stnolting

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

stnolting

Experiments with Cologne Chip's GateMate FPGA architecture

tmeissner

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

wyvernSemi