Viktor Vilhelm Sonesten
Viktor Vilhelm Sonesten
> and use [`*_unchecked`] in the safe version after doing all of the checking Only possible with features that have their own feature flag field, e.g. `NOCYCCNT`. `GTSFREQ` is RAZ/WI...
@adamgreig any updates on the svd2rust generation? Is there a tracking issue for it?
old openocd debug notes regarding `FFCR`: `TPIU_FFCR`, Formatter and Flush Control Register. See *ARM Cortex-M4 Processor Technical Reference Manual, rev. r0p1, p. 95*: Clears `EnFCont`: disables continuous formatting. That is,...
[`FFCR` is part of the Cortex-M4 platform](https://developer.arm.com/documentation/ddi0439/b/Trace-Port-Interface-Unit/TPIU-programmers-model). I do not know what other Cortex-M platforms support it, but a `cm4` feature gate should be added.
[`FFCR` is also a part of the Cortex-M7 platform](https://developer.arm.com/documentation/ddi0489/f/cortex-m7-trace-port-interface-unit/tpiu-programmers-model).
[`LAR` (and `LSR`) are CoreSight managenment registers](https://developer.arm.com/documentation/ddi0403/d/Appendices/ARMv7-M-CoreSight-Infrastructure-IDs/CoreSight-infrastructure-IDs-for-an-ARMv7-M-implementation?lang=en#Cjabefdi). `LSR` is RAZ if not implemented so I presume we can sefely use it without a gate. `LAR` and `LSR` usage is described...
dc4642512761f2b6d9fe65d7878cd12a2131aeb8 can be fixup'd into 622a9b7297f47a1d6a0d40894e2d2994ad46db27.
Wait with eventual merge for me to test these checks. It should be done by next week.
https://github.com/rust-embedded/cortex-m/issues/392 must be handled in this PR.