Cheng Tan

Hi 1bing2, The timing can be estimated by your synthesis technology (through some pre experiment on each basic operation before model an entire CGRA). Say, 45nm, mul might be 0.6ns,...

Can you pull the latest mapper in the docker and try it again? You can make a 2x2 CGRA and then try to uncheck some functionality. Then the performance change...

> Hi ,cheng Where can I generate or obtain the MRRG of CGRA? Thank you! Have a nice Day! Hi, there is no visualization of MRRG but it is create...

Hi, may I know you were running it inside the docker or build it up by urself?

I think there maybe a bug in the docker. Please refer to [this](https://github.com/tancheng/CGRA-Mapper/commit/9cd5280ebac4dbc9946369d2e8e590e8eaa73a7d) to see how to disable/enable each tile's functionality. You can modify the mapper in the docker. I...

Hi, the throughput of a kernel can be obtained by mapping. You can see `II` once the mapping is done, which indicates the initiation interval (execution cycle of each iteration)...

Yes, the total execution time is 128 + some pipeline draining cycles (wait for the final valid output storing in the memory). Yes, writing up your own testbench for the...

> Also for multi-dimensional address generation, the getelementptr cannot be mapped to a simple ADD anymore. Thanks for the input!

Plz check out https://github.com/tancheng/CGRA-Flow