Question about how to obtain evaluation indicators for tasks

[1bing2]

Hi,Cheng, Recently, I was working on the topic of Microarchitecture space exploration based on the OpenCGRA framework, but I encountered some problems. For a. cpp file, we use CGRA Mapper to map it to a specific architecture and generate related files. , but how can we obtain the execution time of the tasks described in the. cpp file in a specific architecture. Have a nice Day! Thanks!

[tancheng]

Hi, the throughput of a kernel can be obtained by mapping. You can see II once the mapping is done, which indicates the initiation interval (execution cycle of each iteration) of the kernel. Roughly, multiply the II with the loop bound should be the execution cycles of the entire kernel.

[1bing2]

Hi, the throughput of a kernel can be obtained by mapping. You can see II once the mapping is done, which indicates the initiation interval (execution cycle of each iteration) of the kernel. Roughly, multiply the II with the loop bound should be the execution cycles of the entire kernel.

Thank you for your quick reply! This means that if my map II is 4, the entire loop will be 32. So my performance time is 128 cycles? By the way, if I want to use hardware simulation, can I manually write a testbench to simulate the generated verilog using data packets? Thank you! Have a nice Day!

[tancheng]

Yes, the total execution time is 128 + some pipeline draining cycles (wait for the final valid output storing in the memory). Yes, writing up your own testbench for the generated verilog sounds a good idea. We are also working on updating the PyMTL3 version to make it possible to automatically generate testbench from the python test. We are also working on refining the PyMTL RTL for the CGRA. Will update you once we have progress.