neorv32-verilog
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♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
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Bumps [neorv32](https://github.com/stnolting/neorv32) from `3d71f3e` to `cb25a4f`. Commits cb25a4f [rtl] remove illegal (escape) character e688424 :warning: rework PWM module (#1049) 517e263 [vivado_ip] increase number of pwm channels 2244ed3 :warning: [rtl] rework...
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