Adrian Sampson

> @sampsyo pointed out that the mux in front of the loop implies a logical time gap (@sampsyo please expand). The issue I was referring to is that putting an...

Very fancy!

Well, speaking purely philosophically and not about this specific case, I think it's a little less cut and dry for us than other compilers… because part of Dahlia's "value proposition"...

Yeah, always working around weird bugs might be infeasible. But I guess I'm just pointing out that the distinction between "weird bugs in this particular version of Vivado HLS" and...

Great writeup! Thanks for crafting a ticket for this frequent discussion point. Here are a few quick notes: - I agree that we should stick with the "inline everything" semantics...

Neat! I do think time steps should indeed replenish function resources, as they do memory banks—the reason being that function calls (unless we do something drastic) are synchronous, i.e., a...

### ""Debug Symbols"" for EDA Failure Diagnosis We'd like to be able to diagnose failures that happen later in the EDA toolchain—i.e., synthesis, technology mapping, and place-and-route—by exposing them in...

### Hardware Externs Take hardware modules, either written directly in Verilog or in some other "generator" language like Chisel, and expose them as `extern`-like functions to Fuse programs. Seen this...

^^ It occurs to me that "c2fuse" (https://github.com/cucapra/seashell/issues/160#issuecomment-477346046) could be construed as a different solution to the same problem of basic language familiarity.

That KNN loop is a good example! To summarize the argument against `break`, from a Dahlia predictability perspective: adding a single line (`break`) inside an unrolled loop introduces extra hardware...