Time-Appliance-Project
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opencomputeproject
Develop an end-to-end hypothetical reference model, network architectures, performance objectives and the methods to distribute, operate, monitor time synchronization within data center and much more....
Time Card starts with a random frequency offset (around 5ppm). It doesn't correct the frequency until it gets the GNSS lock. The issue is shown in the video below. It...
The driver loads but fails to allocate interrupts when connecting the TimeCard to the RPi CM4 2GB and 4GB modules. As a result, no TTY ports are present. The same...
The HighRangAddress of the AXI IIC CLOCK lines are wrong. It is 00120FFF, but that is lower than the Low address. I guess it should be 0020FFFF to match the...
Should the version number in the CoreList match the number in the Version register of that core? There are some that are different. ``` timecard0: CoreList 0x10000, register 0x10001, TC...
There are lot of vias in pads, should we fill them with resin? If yes, should we fill all vias with resin or just fill vias in pads with resin?...
Ref. schematic R4006-G0001-03-SC-REV02.pdf If using the USB interface (FT432, sht. 24), the FPGA JTAG signals are double-terminated by resistors shown at sht. 24, zone B11: >  and sht. 10,...
/Time-Card/OSC)/LOF Spec v01.docx sections 5.3.1 and 5.3.2 are incomplete (and one dimension is incorrect). Assuming the Microchip Technology MAC-SA5x is the template, then the following drawing is closer to what...
Time-Card/OSC/HW/SA45 Daughtercard/Latest)/SCH_SA45_DaughterCard.pdf does not connect the BITE output (SA45) or "Lock Indication" (IQP_ICPT1) to the LOCK pin (P6).
The production board schematic description on sht. 1 says "X4 PCIE TIME CARD", and four lanes are routed between the edge connector and FPGA (schematic and board). However, the production...
The transient voltage suppressors (TVS), IC's CR4 and CR5 (schematic sht. 23, D12 and H12) are not connected to +3.3V (net XP3R3V_FPGA), thus offer no protection for the '125 buffers...
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Develop an end-to-end hypothetical reference model, network architectures, performance objectives and the methods to distribute, operate, monitor time synchronization within data center and much more....