Muhammad Aldacher
Muhammad Aldacher
Layout-Design-of-an-8x8-SRAM-array
The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Nois...
Analog-Design-of-1.9-GHz-PLL-system
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC
This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipel...
Analog-Design-of-Asynchronous-SAR-ADC
This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.
Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp
This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
RF-design-of-1.9-GHz-Rx-frontend
This project shows the design process of the main blocks of a typical RX frontend system.
Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.