riscv-llvm
riscv-llvm copied to clipboard
lowRISC
RISC-V support for LLVM projects (LLVM, Clang, ...)
Currently we avoid emitting jump tables at all by setting `setMinimumJumpTableEntries` to `INT_MAX`.
compiler-rt actually holds code from a number of projects, including: * Various sanitizers (ASan, UBSan, ...) * Scudo * XRay * Compiler primitives (a replacement for libgcc)
See examples of unnecessary `addi` in test/CodeGen/RISCV/{mem,widemem}.ll
See test/CodeGen/RISCV/large-stack.ll. It's hard to imagine this will be a big win in many cases, so consider this a low priority.
It would be really interesting to validate the accuracy of the model against the hardware, and to demonstrate its impact via benchmarks.
This RISC-V base ISA supports only 16 registers. Some details of the ABI plus calling convention change as well. The LLVM side shouldn't be complex, but the definition of the...
This should be relatively mechanical. Some new fixup+relocation types will be needed, and the diasassembler must be taught to disassemble variable-length RISC-V instructions.