riscv-llvm
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lowRISC
RISC-V support for LLVM projects (LLVM, Clang, ...)
Converting a 32-bit instructions to a 16-bit instruction where possible is a good starting point. It may then be worth looking at opportunities for increasing the number of instructions where...
[GlobalISel](https://llvm.org/docs/GlobalISel.html) is a new instruction selection that ultimately aims to replace both SelectionDAG and FastISel. Given that replacing FastISel use cases seems to be an initial focus for the GlobalISel...
Andes [indicated on the mailing list](http://lists.llvm.org/pipermail/llvm-dev/2017-July/115249.html) that they have been working on this.
This task involves: * Determining, and documenting the current RISC-V specific command-line options supported by GCC. Ideally future command-line options can be discussed with involvement from both the GCC and...
A hacky patch in PrologEpilogInserter is currently used (see [here](https://github.com/lowRISC/riscv-llvm/blob/master/0020-Hack-Set-Frame-Setup-Destroy-in-PrologEpilogInserter.patch)). I posted an [RFC](http://lists.llvm.org/pipermail/llvm-dev/2017-February/110281.html) and [illustrative patch](https://reviews.llvm.org/D30115) for fixing this issue in a cleaner way. After further discussion, I [now...
I'll be creating a number of issues today to track remaining work (encompassing work that isn't currently on my personal roadmap, as well as my planned next steps). If you're...
the svn url of llvm is missing. fix it and checkout the commit-04f9bcaa6d3b991266a74360ea1716cfb14e38ea(svn:326957).
