liuqdev.github.io [email protected]
Tsinghua University Beijing Live and learn.
Qi Liu(刘奇)
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
liuqdev
