Jim Huang

[luajit-remake](https://github.com/luajit-remake/luajit-remake) transforms an LLVM function to make it suitable for compilation and back-parsing into a copy-and-patch stencil. The transformation process involves the following steps: The function is split into two...

[Jonathan Müller](https://www.jonathanmueller.dev/) has an excellent talk on [A deep dive into dispatching techniques](https://www.jonathanmueller.dev/talk/deep-dive-dispatch/). He compared the manual jump table and the one generated by optimizing compiler. - [ ] Manual...

[WebAssembly Micro Runtime](https://github.com/bytecodealliance/wasm-micro-runtime) (WAMR) is a lightweight standalone WebAssembly (Wasm) runtime with small footprint, high performance and highly configurable features for applications cross from embedded devices. * [multi-tier compilation framework](https://github.com/bytecodealliance/wasm-micro-runtime/issues/1302)...

Possible lightweight JIT framework: * [TildeBackend](https://github.com/RealNeGate/Cuik/tree/master/tb) (Tilde or TB for short) * [Cwerg](https://github.com/robertmuth/Cwerg) * [dstogov/ir](https://github.com/dstogov/ir) used by PHP

The core of the security concern lies in the inherent complexity of the system. Even extensively used and battle-tested tools like wasmtime have experienced severe vulnerabilities, such as the recent...

> * [dstogov/ir](https://github.com/dstogov/ir) used by PHP An experimental JIT for PHP, built upon [dstogov/ir](https://github.com/dstogov/ir) project, has been developed and can be found in the [master branch](https://github.com/php/php-src/tree/master/ext/opcache/jit) of the php-src repository....

[Whose baseline compiler is it anyway?](https://arxiv.org/abs/2305.13241) by Ben L. Titzer > We show the design of a new single-pass compiler for a research Wasm engine that integrates with an in-place...

The concept of [delay slot](https://en.wikipedia.org/wiki/Delay_slot) in MIPS was initially a straightforward solution to manage pipeline hazards in five-stage pipelines. However, it became a challenge for processors with longer pipelines and...

[rv64_emulator](https://github.com/WadeGao/rv64_emulator) is a RISC-V ISA emulation suite which contains a full system emulator and an ELF instruction frequency analyzer, with JIT compiler for Arm64.

How can you test the RVV instructions?