Jim Huang

I tend to close this pull request since modern compiler optimizer can always generate good code. There is no need to apply such proposed change.

> This PR is not fully ready to be merged since testing is not yet fully designed. PR earlier to get some feedbacks for further design. How can we test...

> 1. Creating a simple userspace application and kernel supervisor > 2. Starts executing with the simple kernel supervisor. Read/write CSR register to install exception vector table to specific address...

> During block emulation, I think the instructions are executed sequentially until block ends. As such, when a page fault exception is generated during block emulation, the RISC-V core has...

> Steps to reproduce the VM test: > 1. `make ENABLE_SYSTEM=1` > 2. Go to the tests/system directory, run `make` > 3. `build/rv32emu tests/system/vm.elf` At first glance, it appears that...

> If the execution flow like this `0x800000b0 -> 0x800000b4 -> 0x800000b8 -> ... -> 0x4 -> 0x8 -> ...`, there will no instruction fetch page fault generated since the...

> In this [section](https://github.com/qemu/qemu/blob/d16cab541ab9217977e2a39abf3d79f914146741/target/riscv/cpu_helper.c#L1427), we can see that if the MMU generates fault, the former is called then latter is called. We could possibly need to provide such similar mechanism...

RISC-V Architecture Test complains: > ERROR | rv32emu/tests/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/ecall.S : - : Failed

Quote from the comment of [esp32-running-linux](https://github.com/nodestark/esp32-running-linux/blob/main/riscv-esp32s3r8/main/riscv-esp32s3r8.c) > The TLB is a high-level cache of the page table, which stores the most recently used translations and makes them quickly and efficiently...

I defer to @vacantron for confirmation.