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Intel staging area for llvm.org contribution. Home for Intel LLVM-based projects.
Continuation of the refactoring in https://github.com/intel/llvm/pull/18795 https://github.com/intel/llvm/pull/18877 https://github.com/intel/llvm/pull/18966 https://github.com/intel/llvm/pull/18979 https://github.com/intel/llvm/pull/18980 https://github.com/intel/llvm/pull/18981 https://github.com/intel/llvm/pull/19007
This change extracts handleESIMD from sycl-post-link to SYCLPostLink component for reuse in NewOffloading compilation flow in clang and for reuse in sycl-jit. The body of `handleESIMD` function is refactored for...
This doesn't update all the instances but it's self-contained and it would be easier to review if I'll submit other changes separately. This is relatively big already. This set of...
Add TargetInfo for MSVC ARM64 host with SPIR64 or SPIRV64 device target.
### Describe the bug Example run: https://github.com/intel/llvm/actions/runs/15544819604/job/43765014831 The failure only seems to happen when test-suite is run in parallel and when copy-oflload is enabled. I wasn't able to reproduce it...
by using multiple in-order queues and round-robin strategy to dispatch work. With this approach we don't need to worry about events' lifetime. Since we are still using counter-based events, we...
Make `slicePitch` equal to image size and `numSlices` 1 for a 2D image. This was incorrect but wasn't failing as many backends ignore `Pitch[1]` for a 2D image.
The `-fsycl-device-lib-jit-link` only has an effect in SPIR compilation so these tests would fail with `-Werror` for non SPIR targets. This basically the same as #18985, but also apply it...
