fpga-network-stack

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How to generate bitstream (wiki is outdated)

19

I've been trying to generate the bitstream targeting VCU118 for benchmark purposes. To generate the bitstream, [the wiki](https://github.com/fpgasystems/fpga-network-stack/wiki/Getting-Started-Guide) says to run Vivado using `create_vcu118_proj.tcl`, which is now located in `scripts`...

lomotos10

Hi @dsidler , I'm using the rocev2 IP and I'd like to test its bandwidth or latency. However, I don't see how to access the QP states so as to...

hcxxstl

Is it possibel to support xilinx kc705 or kcu105 board?

3

Hi, expert: Is it possibel to support xilinx kc705 or kcu105 board?

hushunkui

Hi guys, your project is great. I know this question is rhetorical but I’m trying to get started with a VCU 707 board and was wondering if your code is...

noelpedro

Not sure if some directories or files are updated to different versions causing this error. But we found in the *project.tcl , it sets the src_dir to "rtl", but there...

torukskywalker

I just found the dcp file for SmartCamctl. Do you have the source file for it? C file or rtl file are both ok.

TomHuangsrc

Could you share me the dcps which can be opened by vivado2019.1 ?

xiaoliang201188

can you also please provide the test vectors for the RoCE module? Thank you !!

1

Hi David, can you also please provide the test vectors for the RoCE module (or the corresponding scripts to generate such test vectors)? In the script they should be write_read_read_large_receiver.in...

hao310rui140326

TCP windows size exeded then stall

1

Hi, I adapted your code to run on the KC705 at 10Gbps. I tested ping, echo server, PC to FPGA custom data transfer and it work fine so far. I...

Thales2

added - `ip_handler_top` decl in the header - renamed test file as in the generated make.tcl w/o these 2, default `cd hls/ip_handler; make csim` will not not work. (after cmaking)...

vkhristenko