Alexander Monakov

> However, the pbuffer is still necessary to have a windowless GL context. This is technically not true at least in the context of GLX starting from OpenGL 3.0; quoting...

OK, thanks for your clarifications; regarding pbuffers on nvidia, I'm using pbuffers on nvidia side in primus and there were no problems like that; I'm inclined to think it's either...

The problem I'm trying to draw the attention to is that, in the context of Github issue tracker, offering that quote bare without any further elaboration is not productive. And...

Quoting "This option is evil" is giving feedback on the use of Beamer (which is more appropriate to discuss on StackOverflow-like sites), not on a specific issue in Beamer that...

AMD actually documents this: it's called CPB ("core performance boost"), its presence is testable via cpuid, and can be toggled via the HWCR MSR. It's documented in Zen PPR documents,...

Note that Linux is now filtering userspace MSR writes, with just one MSR allowed at the moment: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/x86/kernel/msr.c?id=a7e1f67ed29f0c339e2aa7483d13b085127566ab The good news is that on AMD systems the acpi-cpufreq driver exposes...

> Ugh, yes, this definitely makes this trickier. Do you know in which kernel version this starts? I haven't run into it yet, but I saw the news on lwn...

Oh, and ```nasm loop: mov edi, [rsp] dec ecx mov [rsp], edi nop nop nop nop nop nop nop nop nop nop nop nop jnz loop ``` is even faster:...

It's also possible to have two interleaved chains, each forwarded in exactly 4 cycles on Sandybridge, though I didn't manage to add a third one: ```nasm mov eax, [rsp] mov...

Apparently this got improved in Ivybridge, as not just three, but four interleaved 4-cycle chains are easily achieved: ```nasm loop: mov eax, [rsp] mov [rsp], eax nop nop mov edx,...