Matthias Koch

We are working on it: https://github.com/ulixxe/usb_cdc/issues/1

Hi Bruno, this one works perfectly now: https://github.com/ulixxe/usb_cdc I already have ported Mecrisp-Ice (my Swapforth/J1a descendant) to the FOMU using the @ulixxe code for terminal, and I can recommend it....

Bonus points for allowing different clocks for USB and for the rest of the logic. Furthermore, it is very compact and it does not need any BRAM blocks.

See https://github.com/ulixxe/usb_cdc, included here for a complete example: https://sourceforge.net/projects/mecrisp/files/mecrisp-ice-2.2.tar.gz/download mecrisp-ice-2.2/fomu/icestorm/j1a.v mecrisp-ice-2.2/common-verilog/usb_cdc/ Done :-)

``` // ###### USB-CDC terminal ############################## assign usb_dp_pu = resetq; wire usb_p_tx; wire usb_n_tx; wire usb_p_rx; wire usb_n_rx; wire usb_tx_en; SB_IO #( .PIN_TYPE(6'b 1010_01), // PIN_OUTPUT_TRISTATE - PIN_INPUT .PULLUP(1'b 0)...

Hi, welcome to the group of FemtoRV experimenters! The interrupt line in FemtoRV is designed to trigger on interrupt requests that last for exactly one clock cycle, for example you...

On WMASK multiplexer, the Half1 and Half2 should be 0011 and 1100. In the diagram, both are 1100. Also I think the input to loadstore_addr should be [31:0] instead of...

https://github.com/nand2mario/usb_hid_host

Congratulations, too! What a beautiful compliment to see FemtoRV going ASIC! Both Bruno and me dreamed of silicon before but did not dare. You did! Hat off!

> While Tarik shall add [femtorv32_quark_bicycle](https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark_bicycle.v) and [eduBOS5](https://fpga-ignite.github.io/presentations-pdf/presentation16.pdf) metrics to his GateMate test suite, it would also be very interesting to hear [@BrunoLevy](https://github.com/BrunoLevy), [@trabucayre](https://github.com/trabucayre), [@matthias](https://github.com/matthias) thoughts on this FPGA architecture...