Matthias Koch

@mithro I am missing an human readable output which tells how resources are distributed on the design, to give a better feedback for manual optimisation.

I think this is because the DTR line is used for Reset, and it returns to default when re-inserting the Icestick.

Maybe try to toggle DTR which is connected to reset line?

Thank you for the observations and hints! Are you going to produce an ASIC with the Quark in it? The Quark is designed around using BRAMs as its register set,...

By the way, if I were about to design an ASIC, I would shoot for some very cool analog chip with special optical features :-) Digital design can be done...

When aluShamt has a non-zero value after coming fresh from a short reset pulse, shifting is active, but as the processor starts in WAIT_ALU_OR_MEM state, it will perform up to...

How will you handle memory busy signals when you aim for similiar CPI but with registers in main memory?

You could try a combinatorial piece of logic for short-circuiting the wait for busy/ready signaling depending on the address range. Bruno inserted a short-circuit for sw/sh/sb working this way; if...

Great! I'll keep an eye on your ongoing development efforts. > Do all processors in the FemtoRV32 family use a synchronous GPR register file? At this point in time, yes....

Hi Bruno, I have an USB-Serial core adapted from a mix of USB logic by Luke Valenty, Lawrie Griffiths and David Williams in Mecrisp-Ice. https://github.com/tinyfpga/TinyFPGA-Bootloader https://github.com/lawrie/tiny_usb_examples https://github.com/davidthings/tinyfpga_bx_usbserial See mecrisp-ice-1.9/common-verilog/usb. It's...