Scott Mabin

> I would be happy to know though why hardware atomics cannot work with PSRAM Whilst it's related to the cache/MMU setup, the reason it doesn't work isn't PSRAM is...

From our discussion in the meeting, we need to determine whether enabling `portable-atomic/critical-section` even on targets with native atomics will use a critical section. If it does, we at least...

> As we're using atomic compare_exchange in our multi-core critical section implementation, can we enable portable-atomic/critical-section without things blowing up? Ah I forgot about that, good catch. Fortunately, I think...

Thanks @taiki-e :heart:! > I'm open to adding a new cfg to adjust the behavior here, but do not intend to change the default I think this entirely reasonable, I...

> I think there are two options on what implementation to use: It sounds like using the `critical-section` impl would be more straight forward I think, but if you have...

> Is it safe to call interrupt disable instruction from user code in xtensa-*-esp-idf? For example, RISC-V and Arm usually restrict the use of such instructions in user mode. If...

I think the easier solution to get the perf required and to avoid unsafe is to store the flash buffer inside `FlashStorage` itself? This way it's only initialized once, and...

Thanks for making us aware of this, I've opened https://github.com/esp-rs/esp-hal/issues/3009 so we don't forget about this. I'm closing this PR now, please feel free to open a new one if...

I agree, but we still need to track the linker script work - we all know how fun they are :D. Could you open a new issue for that, and...

> IMHO we should instead do new().with_config() but the compiler will first apply a default config so it's slightly less efficient... But I think I prefer the code bloat over...