Scott Mabin

> LGTM! Also, I will update all the VMs to use the latest probe-rs as C6 has an older revision. Thanks! In this case the corrupted control block was a...

I think having an example like this would be really nice too! If someone has some spare cycles, we'd appreciate some help in the form of contributions. We'd be happy...

> Suffice to say, I'd definitely like a #[ram] macro that walked the whole graph! I didn't see an obvious way to implement it, though, since proc macros appear to...

Correct, this can be closed!

You could try playing with patching various values from here: https://github.com/esp-rs/esp-hal/blob/4d87e75d71b55d546b37aff6a4494cefb743c4a9/esp32s3-hal/src/lib.rs#L76-L100 in esp-hal. We have a longer-standing issue around cache configuration here: https://github.com/esp-rs/esp-hal/issues/955. Edit: for the other chips, I believe...

@mbq you may wish to test with #430, on RISCV at least I was seeing 2MB/s upload speeds. It seems there are still some bottlenecks on Xtensa though.

@vinc I've updated nightlies up to dec 2019 in #30, you can use my fork until its merged.

@jethrogb Sure, I'd be happy to help maintain this.

@jethrogb Would it be possible to get that invite?

We have plenty of async examples in esp-hal, and esp-wifi. As well as some projects in awesome-esp-rust. Would be nice to support generation here though, but it gets a bit...