Vadim Kaushan

Thanks! However, I think that it's better to describe how to add it to `PATH`. If you change `.cargo/config` this change will make your project not portable (difficult to run...

@laanwj I'm trying to implement SPI support at the moment. For PWM you need to use [Pwm](https://docs.rs/embedded-hal/0.2.2/embedded_hal/trait.Pwm.html) and [PwmPin](https://docs.rs/embedded-hal/0.2.2/embedded_hal/trait.PwmPin.html) traits from the `embedded-hal` crate.

Added SPI example: https://github.com/riscv-rust/riscv-rust-quickstart/blob/master/examples/spi.rs

Yes, but no. `DelayUs` is often used for sub-ms delays, so it's better to use something more precise. You can see one of the examples here: https://github.com/riscv-rust/riscv-rust-quickstart/blob/5ff7048687e807b52d3df0d05dd0729a7c52bf79/examples/spi_wifi.rs#L106-L113, but I'm not...

It's a proof of concept implementation to see how the async traits work in practice. It requires a feature gate (and nightly) to work, so it should be safe to...

I agree that this approach works good for >10MHz (and timer works even better for core frequency

@burrbull `SYSCTL` and `FPIOA` were parsed from the SDK, but `UARTHS` and `GPIOHS` were taken from [`e310x`](https://github.com/riscv-rust/e310x) with minimal changes.

@burrbull You can modify [my script](https://github.com/Disasm/rust-ewg-meta/blob/master/k210/parse-header.py) for this purpose. Automation makes process less boring and error-prone.

@burrbull I'll try to figure out what to do with this, but if there is no way to declare 64-bit register, you can use two 32-bit registers with `_lo` and...

I'm not sure either. I see at least one major problem: such half-accesses may be forbidden in hardware, but this behavior can be checked.