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Dear developer, In your use case of LinearAttentionTransformerLM, dim != dim_head * heads. I am a little bit confused about that. Is that an algorithm feature?

Can I simulate the accelerator whose clock frequency is larger than 1GHz

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Hello, I think in the current framework. The cycle time of the accelerator is stored as integers, so the max accelerator clock frequency is 1GHz. Is it possible to simulate...

Does RWKV-4 music use the RWKV-v4 network architecture?

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Hi, I wonder whether the network architecture of RWKV-4-music and RWKV-v4 are the same.

Can RWKV-v4 handle summarization tasks?

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Dear developers, I want to use ROUGE to benchmark RWKV-v4 in some summarization tasks. Is it suitable? model: RWKV-4-Pile-1B5-20220903-8040

Dear Author, While conducting a single core sequential memory read-only test on LPDDR5 6400, I noticed that the system bandwidth is constrained by cache performance with all default settings, rather...

Question about clock ratio

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Dear all, In the standalone mode, there is a parameter called clock ratio. I want to know whether it uses the clock of memory or memory controller. For example, if...

Hi, in your SimpleO3 llc.cpp, each cache miss will issue a single read. So I assume each read is a 64 bytes read. However, I find that in many DDR...