Intel FRED instructions: ERETS, ERETU, LKGS

[tremalrik]

Intel has fairly recently posted a draft specification ( https://software.intel.com/content/dam/develop/external/us/en/documents-tps/346446-flexible-return-and-event-delivery.pdf ) for its planned FRED ("Flexible Return and Event Delivery") x86 ISA extension. This specification lists three new instructions:

• ERETS (F2 0F 01 CA)
• ERETU (F3 0F 01 CA)
• LKGS r/m16 (F2 0F 00 /6)

Neither xed nor Zydis appear to recognize any of these yet - which I suppose raises the question: should these instructions be added to Zydis straight away, or should they be withheld until the specification is finalized and/or a product with FRED is announced?

(AMD has also posted a draft for its own specification covering similar ground - the AMD Supervisor Entry Extensions - however this one does not appear to actually add any new instructions, so there doesn't seem to be anything to do here.)

[flobernd]

Thanks for pointing out the Intel draft.

Usually we wait until XED publishes new ISA extensions, because that usually means they are in a final state and will be used in an upcoming product of the next years.

Other than that, I'm not too concerned to add this specific ISA extension right away. These 3 instructions are easily removed/modified if anything changes on Intel side.