loongarch: Scaffold self-hosted LoongArch backend

[xtexx]

This PR adds a self-hosted LoongArch64 backend.

The backend currently implements only a few features.

Test runner is working, but due to the very limited number of passing behavior tests, the backend is not added to the test target list.

Although it is foreseeable that I will not have much time to work on this backend in the coming one year due to my study, I will try to keep the backend working and expand its features.

[xtexx]

No, it also generates encoders for LA32(S/R). Thank you for looking into this PR. I will rename this file next weekend as soon as I am available.

[alexrp]

cc @jacobly0 to review the general structure of the new backend.

[jacobly0]

You might want to git mv src/arch/loongarch64 src/codegen/loongarch now to avoid annoying conflicts when somebody else does it later.

[xtexx]

I had just force-pushed to rebase onto master, moving src/arch/loongarch64 to src/arch/loongarch, adding basic support for LA32.

[alexrp]

RISC-V CI failures seem related.

[xtexx]

They should be addressed once rebased onto https://github.com/ziglang/zig/pull/24180

[alexrp]

Needs a rebase (due to writergate?).

[alexrp]

FYI, we're in the process of purchasing a Loongson 3C6000/S machine for CI, so merging this will probably have to wait until we have that up and running.

[alexrp]

We have a machine now:

$ lscpu
Architecture:                loongarch64
  CPU op-mode(s):            32-bit, 64-bit
  Address sizes:             48 bits physical, 48 bits virtual
  Byte Order:                Little Endian
CPU(s):                      32
  On-line CPU(s) list:       0-31
Model name:                  Loongson-3C6000
  CPU family:                Loongson-64bit
  Model:                     0x10
  Thread(s) per core:        1
  Core(s) per socket:        32
  Socket(s):                 1
  BogoMIPS:                  4400,00
  Flags:                     cpucfg lam ual fpu lsx lasx crc32 complex crypto lspw lvz lbt_x86 lbt_arm lbt_mips
Caches (sum of all):
  L1d:                       2 MiB (32 instances)
  L1i:                       2 MiB (32 instances)
  L2:                        8 MiB (32 instances)
  L3:                        32 MiB (1 instance)
NUMA:
  NUMA node(s):              1
  NUMA node0 CPU(s):         0-31
Vulnerabilities:
  Gather data sampling:      Not affected
  Ghostwrite:                Not affected
  Indirect target selection: Not affected
  Itlb multihit:             Not affected
  L1tf:                      Not affected
  Mds:                       Not affected
  Meltdown:                  Not affected
  Mmio stale data:           Not affected
  Old microcode:             Not affected
  Reg file data sampling:    Not affected
  Retbleed:                  Not affected
  Spec rstack overflow:      Not affected
  Spec store bypass:         Not affected
  Spectre v1:                Not affected
  Spectre v2:                Not affected
  Srbds:                     Not affected
  Tsa:                       Not affected
  Tsx async abort:           Not affected
  Vmscape:                   Not affected
$ lsmem
RANGE                                  SIZE  STATE REMOVABLE BLOCK
0x0000000000000000-0x000000001fffffff  512M online       yes     0
0x0000000080000000-0x000000207fffffff  128G online       yes 4-259

Memory block size:                512M
Total online memory:             128,5G
Total offline memory:               0B

Still some infra stuff to do on our end to get it hooked up to CI, but just wanted to let you know that things are coming along.

[xtexx]

Yeah! On my side I am going to rewrite this PR (while it may take another some months).

[alexrp]

I'm assuming most people have noticed by now, but just for the record, the LoongArch CI machine is running over on Codeberg: https://codeberg.org/ziglang/zig/actions/runs/107/jobs/2/attempt/1

So you'll want to open this PR over there when you get back to it.

[xtexx]

Thanks for the hint. I am currently working on the rewrite of this PR which will still take some time to finish.