Can't build a working program for MIPS32 mips-linux-musl target triple with `zig cc`

[InBetweenNames]

Zig Version

0.13.0

Steps to Reproduce and Observed Behavior

Hello Zig team!

Thanks for continuing to maintain such a fantastic project.

I tried to build and run a simple hello world C program using zig cc and have encountered a problem in the init code in musl when building for MIPS32BE, target triple mips-linux-musl.

The program (main.c):

#include <stdio.h>
int main() {
   printf("Hello, World!\n");
   return 0;
}

The compile line:

zig cc -target mips-linux-musl -mcpu=mips32r6 main.c -o main

To run:

qemu-mips -cpu mips32r6-generic main

Note that MIPS32R5 and below seem to work just fine.

I looked at the generated output and it seems that the symbol _init has an instruction that isn't valid MIPS32R6 in there, which should be a jump. The instruction machine code is 0x03e00008 which should be a JR $ra. Unfortunately, all of my tools are failing to decode this in the binary for MIPS32R6. I haven't dug deeper yet to see why this is, but it does appear to be something going wrong in the musl compilation for this target. -none target triples seem to work fine.

Any advice on how I can debug this further? I understand MIPS32R6 changed or removed some instructions relative to previous revisions and I suspect something like that is going on.

Thank you very much!

Expected Behavior

The program should print Hello World! and exit successfully.

[kassane]

@InBetweenNames, zig code run? Please, try: https://github.com/kassane/riscv64-hello-linux/blob/hello-zig/src/main.zig

Possible output

$/tmp/cpu_info 
Zig Info:

Version: 0.13.0
Stage: stage2_llvm

Let's have a look at your shiny MIPS - mips32r2 system! :)

cpuinfo:
system type             : MediaTek MT7628AN ver:1 eco:2
machine                 : TP-Link TL-WR840N v4
processor               : 0
cpu model               : MIPS 24KEc V5.5
BogoMIPS                : 385.84
wait instruction        : yes
microsecond timers      : yes
tlb_entries             : 32
extra interrupt vector  : yes
hardware watchpoint     : yes, count: 4, address/irw mask: [0x0ffc, 0x0ffc, 0x0ffb, 0x0ffb]
isa                     : mips1 mips2 mips32r1 mips32r2
ASEs implemented        : mips16 dsp
Options implemented     : tlb 4kex 4k_cache prefetch mcheck ejtag llsc pindexed_dcache userlocal vint perf_cntr_intr_bit perf
shadow register sets    : 1
kscratch registers      : 0
package                 : 0
core                    : 0
VCED exceptions         : not available
VCEI exceptions         : not available

meminfo:
MemTotal:          57620 kB
MemFree:           30744 kB
MemAvailable:      24476 kB

cmdline:
console=ttyS0,115200 rootfstype=squashfs,jffs2

kernel:
Linux OpenWrt 5.10.138 #0 Sat Sep 3 02:55:34 2022 mips GNU/Linux

[alexrp]

This is an LLVM assembler bug.

❯ cat test.s
.global __start
__start:
    j $ra
❯ clang -target mipsisa64r6-linux-gnu -nostdlib test.s
❯ objdump --disassemble=__start a.out

a.out:     file format elf64-tradbigmips


Disassembly of section .text:

00000000000003f0 <__start>:
 3f0:   03e00008        .word   0x3e00008
 3f4:   00000000        nop
❯ mips64-linux-gnuabi64-gcc -march=mips64r6 -nostdlib test.s
❯ objdump --disassemble=__start a.out

a.out:     file format elf64-tradbigmips


Disassembly of section .text:

0000000120000150 <__start>:
   120000150:   03e00009        jr      ra
   120000154:   00000000        nop
        ...

[alexrp]

https://github.com/llvm/llvm-project/issues/107460

[alexrp]

https://github.com/ziglang/zig/pull/21441 will work around this on our side. This bug should remain open to track removing the workaround when the LLVM assembler bug is fixed.