llvm: `@Vector(4, u80)` parameters trigger an assertion on aarch64 with optimizations disabled

[jacobly0]

zig: llvm/lib/CodeGen/GlobalISel/CallLowering.cpp:466: void buildCopyFromRegs(MachineIRBuilder &, ArrayRef<Register>, ArrayRef<Register>, LLT, LLT, const ISD::ArgFlagsTy): Assertion `DstEltTy.getSizeInBits() % PartLLT.getSizeInBits() == 0' failed.
    frame #5: 0x00007fffdafce1e6 libLLVMGlobalISel.so.18.1`buildCopyFromRegs(B=0x0000000008c43640, OrigRegs=ArrayRef<llvm::Register> @ 0x00007ffffffe7228, Regs=ArrayRef<llvm::Register> @ 0x00007ffffffe7218, LLTy=(IsScalar = 0, IsPointer = 0, IsVector = 1, RawData = 5242884), PartLLT=(IsScalar = 1, IsPointer = 0, IsVector = 0, RawData = 64), Flags=llvm::ISD::ArgFlagsTy @ 0x00007ffffffe7658) at CallLowering.cpp:466:5
    frame #6: 0x00007fffdafcbb7f libLLVMGlobalISel.so.18.1`llvm::CallLowering::handleAssignments(this=0x000000000448ac80, Handler=0x00007ffffffe7e90, Args=0x00007ffffffe82d8, CCInfo=0x00007ffffffe7ef8, ArgLocs=0x00007ffffffe8070, MIRBuilder=0x0000000008c43640, ThisReturnRegs=ArrayRef<llvm::Register> @ 0x00007ffffffe7bc0) const at CallLowering.cpp:863:7
    frame #7: 0x00007fffe59ace51 libLLVMAArch64CodeGen.so.18.1`llvm::AArch64CallLowering::lowerFormalArguments(this=0x000000000448ac80, MIRBuilder=0x0000000008c43640, F=0x00000000047055e8, VRegs=ArrayRef<llvm::ArrayRef<llvm::Register> > @ 0x00007ffffffe7e30, FLI=0x0000000004835438) const at AArch64CallLowering.cpp:705:8