Haozhe Zhu

Hi, do we have a solution now? (excepts regex) I am generating two designs (one for FPGA and the other for ASIC) with some common codes. and I have to...

@ekiwi Cool. Thanks a lot.

@Dolu1990 has presented a workaround in the Gitter chat channel. ```scala val x = HardType(new Bundle{ ... })() ```

I am using anaconda environment. Here is the package list. ``` # packages in environment at /home/hzzhu/Software/anaconda3/envs/tensorflow: # # Name Version Build Channel absl-py 0.7.0 pypi_0 pypi astor 0.7.1 pypi_0...

I am running the code on Ubuntu 18.04 LTS, with CUDA10. The graphic driver is the default one which is attached to the CUDA installation package.

I tried `gdb python core`. Here is output in the console. ``` $ gdb python core GNU gdb (Ubuntu 8.1-0ubuntu3) 8.1.0.20180409-git Copyright (C) 2018 Free Software Foundation, Inc. License GPLv3+:...

> I got same error with example command. did you solve it? Sorry, not yet. If you have any idea, I can have a try. @dhkwon1122

For example, I have a SystemVerilog module like this: ```SystemVerilog module Test #(parameter W = 16)( input wire [1:0][W-1:0] a, ... ); ... ``` The input port `a` in this...

I have tried to install from homebrew, or compile from the code. But neither works (same error during compilation). If you can compile one on the CI, I will be...

Hi @hzeller , thanks for you quick reply. I recompiled today. It looks a bit different two days ago (still fail but other bugs). See below: I am not familiar...