Dynamic Arrays support

[MrJake222]

Hi,

I'm trying to convert pequeno_riscv to Verilog and it fails here:

function automatic void dump_regfile (int fdump, int n, logic [RSIZE-1:0] regarray [], string dumpname);

Are dynamic arrays a no-go when converting to Verilog? I guess so, without language support it'd be difficult to handle.

[zachjs]

Indeed dynamic arrays are neither synthesizable nor easily converted into Verilog. Are you using sv2v as part of synthesis flow, or something else? One possibility: If this code is in a common package that you don't need, perhaps sv2v could "pass through" dynamic arrays, under the assumption they won't be used downstream.