Would you please implement those enum methods for SystemVerilog ?

[forthyen]

like this

// Element width typedef enum logic [2:0] { EW8 = 3'b000, EW16 = 3'b001, EW32 = 3'b010, EW64 = 3'b011, EW128 = 3'b100, EW256 = 3'b101, EW512 = 3'b110, EW1024 = 3'b111 } vew_e;

// Vector type register typedef struct packed { logic vill; logic vma; logic vta; vew_e vsew; } vtype_t;

module top ( );

vtype_t a; vew_e b;

initial begin a = 6'h0; b = a.vsew; b = a.vsew.next(); end;

endmodule;

Thanks,

[zachjs]

Thanks for filing this request! I have started work on adding support for this feature. It may be a week or so before it is ready.