Qiang Yu

So does increase LIMA_CTX_PLB_BLK_SIZE to 1024 solves the error on your side?

OK, maybe there's other place need to be configured for 1024 PLB like the DLBU reg: https://github.com/yuq/mesa-lima/commit/1c7700fb32a5974867b10da2088da2d3790699b6#diff-15af9d78941ee5e81caea488e2910f77R1092 I just hard code 0x20000000 for 512 PLB, 1024 PLB should be 0x30000000....

From your dump, although the gp stream mem is missing, I can see in the pp stream mem it's still 512 PLB. But I also find in the code that...

OK, then seems not the plb size problem. As the texture, Is it caused by the compiler: https://www.mail-archive.com/[email protected]/msg189216.html

The compiler scalar back to vec problem will get worse when 18.1. But I want to focus on kernel currently so left it with some incomplete work around. The issue...

I don't know if it's proper to always set switch delay to 0xffff as some platform just set this value to 0xff and some set it to 0xffff in the...

Are you sure the switch delay reg is set to 0? this is the min delay or no delay from the comment.

Then if set to 0 in lima kernel driver, does it fix your pp error too?

Progress update: 1. switch to use TTM as MM is done, but I left the buffer eviction and swap not implemented because I don't know if GP/PP support MMU fault...

@anarsoul no problem.