Support RISC-V SIMD/Vector extension

[davidbrochart]

It could be interesting to support RISC-V SIMD or Vector extension. The latter looks very promising as the vector length and data type can be changed at run-time, and is generally considered more efficient than packed-SIMD.

[davidbrochart]

I guess we could start by using Spike, a behavioral RISC-V simulator that supports the V extension.

[davidbrochart]

Renode also supports the V extension now.

[pavitrar20]

I am interested in collaborating on this. Has any work been done?

[davidbrochart]

Not yet, your contribution would be very welcome!

[pavitrar20]

I appreciate pointers on how to get started. I am more of a firmware person- but am interested in using RISC-V SIMD extension for an application

[davidbrochart]

Maybe run an xtensor program on Spike or Renode?

[pavitrar20]

Has anyone run an xtensor program on Spike?

I am able to independently compile a hello program with riscv64-unknown-elf-gcc and use spike pk hello to display

And also use G++ with C++14 to compile xtensor and xtl first program(given in the xtensor page) and run it like a g++ program. But, Spike would not recognize this as a loader file when just compiled with g++.

The platform - Apple MAC M2

[davidbrochart]

Has anyone run an xtensor program on Spike?

I think you're the first one to attempt running xtensor on a RISC-V simulator @pavitrar20 !

I am able to independently compile a hello program with riscv64-unknown-elf-gcc and use spike pk hello to display

I think you need to do the same with xtensor. Compiling xtensor with g++ on your (real) machine and running it in the RISC-V simulator won't work. A simple xtensor program doesn't link with any external library, so you should have all the sources to compile it for RISC-V. What issue are you seeing?

[pavitrar20]

1. I tried it in ubuntu 20.04 LTS . riscv64-unknown-elf-gcc seems to have some documented issues

Basicallly, Ubuntu has binutils and gcc packages for riscv64-unknown-elf, but no libraries. A simple program hello cannot really compile with riscv64-unknown-elf-gcc but can be with just gcc.!

3. I tried on Apple MAC M2 based platform Here a simple compilation works - Work % riscv64-unknown-elf-gcc hello.c -o hello
   Work % spike pk hello bbl loader Hello RISC-V ISA Simulator!!

But a riscv64-unknown-elf-g++ with xtensor did not build when xtensor and xtl were compiled from source with cmake but in a directory /tmp/build.

Work % riscv64-unknown-elf-g++ --std=c++14 -I /tmp/build/xtensor -I /tmp/build/xtl firstTest.cpp -o example firstTest.cpp:2:10: fatal error: xtensor/xarray.hpp: No such file or directory 2 | #include <xtensor/xarray.hpp> | ^~~~~~~~~~~~~~~~~~~~ compilation terminated.

My thoughts are to build xtensor and xtl in the same directory at the same level. And try.

I compiled and built xtensor and xtl as follows- cd /tmp/build cmake -DCMAKE_INSTALL_PREFIX=/usr/local . cd /tmp/build/xtl make install

As you see I have all the sources. Does the above compilation steps amount to compiling for RISCV?

[serge-sans-paille]

Thanks @pavitrar20 for giving it a try. Please note though that there's no need to go through xtensor to implement xsimd support ;-) If you don't enable XTL complex (which is probably better for starters) this should be as simple as creating a sample program, say:

#include <xsimd/xsimd.hpp>
#include <iostream>
int main() {
   xsimd::batch<float> x(1.f), y(2.f);
   sdt::cout << (x + y) << std::endl;
   return 0;
}

compiled with riscv64-unknown-elf-g++ --std=c++14 -Iinclude test.cpp -o test assuming you're in xsimd source. This should fail on an architecture check :-)

[pavitrar20]

Yes, It did fail on Architecture check

[pavitrar20]

Updating status- while compilation succeeds in xsimd lib as well as for other generic tests , using "pk" is inconsistent- This is where I am at - spike []/pk test.cpp for example either leads to a silent hang or a verbose failure (bad syscall). There are open issues of several types. Trying to understand this and resolve at the moment.

[](url) ](https://github.com/riscv-software-src/riscv-tools/issues/324)

[[[]](https://github.com/riscv-software-src/riscv-tests/issues/207)]())(

Tried compiling for 32 bit variants but pk displays error [[]](https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1087)(url)

Andrew Waterman recommends not to use pk and to directlty run on spike but it is not clear how to print messages without pk (a JTAG emulator is not available)

[davidbrochart]

Thanks for the update @pavitrar20, looks like you're making progress. Another option would be to simulate an RTL model of a RISC-V SoC, but I don't know if there are open-source CPUs that implement the vector extension. Then you could directly inspect internal signals of the CPU and see if things are indeed executed in parallel. But that would probably be a bigger work.

[pavitrar20]

Hang on! I may have access to a vector CPU soon for some other work. It can also be repurposed for this. Perhaps inspection could happen through JTAG- I will update on this as soon as I know more.

[luhenry]

Hello, I'm currently working on upstreaming a port at https://github.com/rivosinc/xsimd/tree/upstream-rvv. I'll open a PR as soon as I have something (expecting by end of month).

I'm running into 1 test failure, and I'll want to simplify it a bit before.