risc-v: failed to conversion between rvv register type and batch<T> or batch<T, A>

[Ag-Cu]

When using xsimd on the RISC-V platform, I found that converting between RVV register types and xsimd's batch-related types is quite tricky. This might be due to the variable vector length of RVV.

Here is an example of using xsimd on a platform that supports AVX:

#if XSIMD_WITH_AVX2
inline xsimd::batch<int64_t> cvtU32toI64(
    xsimd::batch<int32_t, xsimd::sse2> values) {
  return _mm256_cvtepu32_epi64(values);
}

Such code compiles smoothly. However, on a platform that supports RVV, if a RVV register type is returned, it cannot be smoothly converted into a batch type, here are two simple situation I met before:

https://godbolt.org/z/Gazvx7f98

Here are more information about my work(porting velox to risc-v using xsimd):

https://github.com/facebookincubator/velox/blob/main/velox/common/base/SimdUtil-inl.h

So, how can I elegantly use both xsimd and RVV intrinsics simultaneously?

[serge-sans-paille]

Would that do the trick: https://godbolt.org/z/qxev5d1G4 ?

[serge-sans-paille]

With an alternative, lower level operation: https://godbolt.org/z/1eqs3e8h1

[Ag-Cu]

With an alternative, lower level operation: https://godbolt.org/z/1eqs3e8h1

Thank you, that's really helpful.