============================================ An Asynchronous Verilog Synthesis (AVS) System

This software is distributed under GPL v2.0 or later licenses.

This is an asynchronous synthesis software. It reads in RTL-level Verilog HDLs and trys to partition the design into a globally asynchronous and locally synchronous (GALS) design while implement the asynchronous interface between synchronous islands.

What I have done:

• Provided a command line environment.
• Adopted a SystemVerilog preprocessor from the Verilog-Perl package to handle macros.
• A Verilog parser which can read in synthesizable Verilog features.
• An error report system provide easy error type insertion and display.
• Automatically report all FSMs.
• Automatically report all available partitions.

Package required: GNU Make ( make ) GNU C++ Compiler ( g++ ) C++0x ( g++ -std=c++0x, lambda expression ) Bison ( bison ) Flex ( flex ) GNU Boost Library ( shared_ptr, regex, filesystem, program_options, lexical_cast, format, string, BGL, Spirit ) GNU MP Bignum Library ( gmp, gmpxx ) rlwrap ( rlwrap ) Tcl/Tk ( Tcl/tk 8.4, cpptcl: already embedded ) PugiXML ( v1.2: already embedded ) OGDF ( Open Graph Drawing Framework ) Qt ( v4 )

Install guide: make

Usage info.: bin/avs_shell the command line synthesis environment. use "help" command for help information.

Other info.: This is a part of the EPSRC funded project GAELS (EP/I038306/1).

Any question or request pls write to [email protected]

Dr. Wei Song APT, CS, University of Manchester [email protected] [email protected] http://apt.cs.man.ac.uk/people/wsong/ http://wsong83.weebly.com/

20/05/2013