Returns wrong L2 Cache Associativity on i5-2520M

[lquenti]

In your bug report please include:

• CPU architecture Single i5-2520M in T420, 2 cores, 2 threads per core
• Operating System Ubuntu 20.04.3 LTS x86_64
• Python version Python 3.8.10
• Version of py-cpuinfo 8.0.0

Bug

It shows the wrong L2 Cache associativity. Here is the output of py-cpuinfo:

(testvenv) lquenti in /tmp/test λ python3 -m cpuinfo
Python Version: 3.8.10.final.0 (64 bit)
Cpuinfo Version: 8.0.0
Vendor ID Raw: GenuineIntel
Hardware Raw: 
Brand Raw: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz
Hz Advertised Friendly: 2.5000 GHz
Hz Actual Friendly: 1.9466 GHz
Hz Advertised: (2500000000, 0)
Hz Actual: (1946562000, 0)
Arch: X86_64
Bits: 64
Count: 4
Arch String Raw: x86_64
L1 Data Cache Size: 64 KiB
L1 Instruction Cache Size: 64 KiB
L2 Cache Size: 512 KiB
L2 Cache Line Size: 256
L2 Cache Associativity: 6
L3 Cache Size: 3145728
Stepping: 7
Model: 42
Family: 6
Processor Type: 
Flags: acpi, aes, aperfmperf, apic, arat, arch_perfmon, avx, bts, clflush, cmov, constant_tsc, cpuid, cx16, cx8, de, ds_cpl, dtes64, dtherm, dts, epb, ept, est, flexpriority, flush_l1d, fpu, fxsr, ht, ibpb, ibrs, ida, lahf_lm, lm, mca, mce, md_clear, mmx, monitor, msr, mtrr, nonstop_tsc, nopl, nx, osxsave, pae, pat, pbe, pcid, pclmulqdq, pdcm, pebs, pge, pln, pni, popcnt, pse, pse36, pti, pts, rdtscp, sep, smx, ss, ssbd, sse, sse2, sse4_1, sse4_2, ssse3, stibp, syscall, tm, tm2, tpr_shadow, tsc, tsc_deadline_timer, tscdeadline, vme, vmx, vnmi, vpid, x2apic, xsave, xsaveopt, xtopology, xtpr

What getconf tells me:

lquenti in ~ λ getconf LEVEL2_CACHE_ASSOC
8

What sysfs tells me (watch the shell expansion in the string)

lquenti in ~ λ cat /sys/devices/system/cpu/cpu{0,1,2,3}/cache/index2/{type,level}
Unified
2
Unified
2
Unified
2
Unified
2
lquenti in ~ λ cat /sys/devices/system/cpu/cpu{0,1,2,3}/cache/index2/ways_of_associativity
8
8
8
8

Partial output of cpuid

lquenti in ~ λ sudo cpuid
...
...
   deterministic cache parameters (4):
      --- cache 0 ---
      cache type                           = data cache (1)
      cache level                          = 0x1 (1)
      self-initializing cache level        = true
      fully associative cache              = false
      extra threads sharing this cache     = 0x1 (1)
      extra processor cores on this die    = 0x7 (7)
      system coherency line size           = 0x40 (64)
      physical line partitions             = 0x1 (1)
      ways of associativity                = 0x8 (8)
      number of sets                       = 0x40 (64)
      WBINVD/INVD acts on lower caches     = false
      inclusive to lower caches            = false
      complex cache indexing               = false
      number of sets (s)                   = 64
      (size synth)                         = 32768 (32 KB)
      --- cache 1 ---
      cache type                           = instruction cache (2)
      cache level                          = 0x1 (1)
      self-initializing cache level        = true
      fully associative cache              = false
      extra threads sharing this cache     = 0x1 (1)
      extra processor cores on this die    = 0x7 (7)
      system coherency line size           = 0x40 (64)
      physical line partitions             = 0x1 (1)
      ways of associativity                = 0x8 (8)
      number of sets                       = 0x40 (64)
      WBINVD/INVD acts on lower caches     = false
      inclusive to lower caches            = false
      complex cache indexing               = false
      number of sets (s)                   = 64
      (size synth)                         = 32768 (32 KB)
      --- cache 2 ---
      cache type                           = unified cache (3)
      cache level                          = 0x2 (2)
      self-initializing cache level        = true
      fully associative cache              = false
      extra threads sharing this cache     = 0x1 (1)
      extra processor cores on this die    = 0x7 (7)
      system coherency line size           = 0x40 (64)
      physical line partitions             = 0x1 (1)
      ways of associativity                = 0x8 (8)
      number of sets                       = 0x200 (512)
      WBINVD/INVD acts on lower caches     = false
      inclusive to lower caches            = false
      complex cache indexing               = false
      number of sets (s)                   = 512
      (size synth)                         = 262144 (256 KB)

[lquenti]

If I can further provide information, please just tell me.

[lquenti]

I played around with it a bit further. 8 also makes more sense since we know that

ways_of_associativity * cache_line_size * number_of_sets = size

So here are the values, which do add up from sysfs

lquenti in ~ λ cat /sys/devices/system/cpu/cpu0/cache/index2/{number_of_sets,coherency_line_size,ways_of_associativity}
512
64
8
lquenti in ~ λ cat /sys/devices/system/cpu/cpu0/cache/index2/size                                                      
256K
lquenti in ~ λ python -c "print((512*64*8)/1024)"
256

[workhorsy]

I'll have to look more into this. Sorry I didn't respond earlier, my Internet was not working a over a week.

[lquenti]

Take your time, I wrote a sysfs-wrapper myself for now. I really don't know how those special assembly-instructions work, if you want me anything to execute just write it, as well as any brainstorming ideas.