Ability to Specify Jumpers

[AlanLivingston]

Currently, if I want to jump from a connector pin 3 to pin 4, I have to create a wire set, and in the connections, specify the connection like: connectors: X6: pinlabels: [+28VDC, +28VDC RTN, Token-In REF, Token-In, NC, NC, RS-485+, RS-485-, RS-485 Shield] type: P1 `cables:` ` W5:` ` colors: [BU]` connections: - - X6: 3 - W5: 1 - X6: 4

But this creates a very bulky diagram, when what I really want is a jumper from pin 3 to pin 4 on the left side of connector X6.

[kvid]

I agree the current version (v0.3.2) doesn't handle such loops in the diagram very well, but there is an optional loops attribute you can use for connectors that should fit well in your use case:

connectors:
  X6:
    pinlabels: [+28VDC, +28VDC RTN, Token-In REF, Token-In, NC, NC, RS-485+, RS-485-, RS-485 Shield]
    type: P1
    loops:
      - [3, 4]

See the syntax doc, and also #48 where this feature and some possible alternatives are discussed.

[AlanLivingston]

I missed the loops attribute. That is, indeed, what I wanted.

As mentioned in #48, the length of the shorting wire needs some control. It overlapped the wire description box:

I was able to work around this by reordering the pins:

  X2:   # D369-P99-NS1
    pins: [1, 2, 5, 6, 7, 8, 9, 3, 4]
    pinlabels: [+28VDC, +28VDC RTN, NC, NC, RS-485+, RS-485-, RS-485 Shield, Token-In REF, Token-In]
    type: P1
    subtype: Deutsch D369-P99-NS1 9-Pin Receptacle Connector
    loops:
      - [8, 9]

I had to refer to the loop by the pin index within pins, and not its value. I don't know if this is intended or a bug.

Anyway, I have a suitable solution. Thanks!

[kvid]

I missed the loops attribute. That is, indeed, what I wanted.

👍

As mentioned in #48, the length of the shorting wire needs some control. It overlapped the wire description box:

Suggestions about how to solve this are welcome! The overlap and spline lengths are controlled by the Graphviz dot tool, and I don't know if any of the input parameters of this tool can override such features.

I had to refer to the loop by the pin index within pins, and not its value. I don't know if this is intended or a bug.

I would say it sounds like an unwanted feature.

[riv-david]

A quick hacky solution would be to increase or give control of the spacing for tables such that the loops generated wouldn't overlap them.

moving X2 table 30mm to the right would make this useable

[kvid]

Increasing the horizontal spacing, as suggested by @rr-david, can be done like this:

connectors:
  X2:
    pinlabels: [+28VDC, +28VDC RTN, Token-In REF, Token-In, NC, NC, RS-485+, RS-485-, RS-485 Shield]
    type: P1
    loops:
      - [3, 4]
cables:
  W1:
    colors: [RD, BK, IV, BU, GN]
connections:
  - - W1: [1-5]
    - X2: [1-2, 7-9]
tweak:
  override:
    graph:
      ranksep: "3"  # Increase the horizontal spacing (default 2)

However, be aware that this is a global setting that affects spacing in the whole diagram.

[blackbit42]

Increasing the horizontal spacing is useful for the current implementation of loops as it helps with the wire table not overlapping the loop(s). Though, doing so is only necessary because loops are currently very pronounced... well, loops.

Is there perhaps a clever way to use GraphViz tweaking to influence the appearance of loops?

In case that cannot be done just for loops, I could imagine that a hint to GraphViz not to generally make bends less pronounced on a global level would potentially not hurt regular wires much but improve the appearance of loops.

[kvid]

@blackbit42 wrote:

Increasing the horizontal spacing is useful for the current implementation of loops as it helps with the wire table not overlapping the loop(s). Though, doing so is only necessary because loops are currently very pronounced... well, loops.

How wide the loops become seems to be dependent on other elements in the diagram, their spacing, or some other relations. Compare the small loop in my single connector diagram above with the wider loops in the larger diagrams. This dependency is also mentioned in #288.

The reason behind such a difference has to be connected to the internal algorithms of Graphviz - that I don't know much about. Please search/ask at Graphviz user phorums to investigate further.

Is there perhaps a clever way to use GraphViz tweaking to influence the appearance of loops?

I recommend editing the .gv file to try out possible changes and run it through the Graphviz dot tool to see the result. When you know what to change, then we can see if it can be done with the tweak functionality.

In case that cannot be done just for loops, I could imagine that a hint to GraphViz not to generally make bends less pronounced on a global level would potentially not hurt regular wires much but improve the appearance of loops.

This is a question you should ask at some Graphviz phorum. In #3 you can find some examples on advanced Graphviz attributes for controlling the wire curves in a twisted wire usecase, and in #120 you can find some alternative ways to call Graphviz. Maybe any of those can be of any help.