Catherine
Catherine
No. Take a look at the section of the FX2 manual that describes how loads its firmware from EEPROM. In short, there's a series of length-address-value chunks at the start...
Sorry for the delay, I had my hands full. I'll take a look soon!
Most of the blockers are done. Only the memory write issue remains.
An IRC discussion with @awygle confirmed my suspicion that race-free concurrent operations on memories are not something that has a lot of value, and given the significant amount of effort...
The thought of a "RTL TSAN" crossed my mind, but I do not expect to have time to work on it in foreseeable future.
I'm fairly certain this doesn't actually work in PySim either (the "override" is silently reverted the next time any inputs to the combinatorial function change), so I would classify the...
Though, both PySim and CXXSim need to be fixed: the former so that it is actually an error, the latter so that the error is nicer.
> So Yosys isn't doing anything wrong by assuming that this is a valid way to initialize memories when translating the RTLIL into Verilog to feed to Diamond for synthesis?...
Yes, that's pretty common. We can add a timeout for USB requests, which is already supported by the streaming code we have, and raise an exception in `I2CInitiatorInterface`. The state...
Huh? Why use an adapter if we can just not have one?