Catherine
Catherine
> I agree, that sounds like the best tradeoff right now. And _probably_ the simulator should register a finalizer hook to attempt `aclose`, since that's what event loops are expected...
Oh, the other potential problem is that by capturing the callstack you will prevent any of the objects referenced by any of the frames from being collected before the entire...
At the time I implemented the existing code, I was concerned about the overhead of using `linecache`, since it takes a noticeable amount of time to grab the source code....
By the way, regarding the "first/last wins" discussion: one caveat is that the same file can appear in the traceback multiple times, potentially in between two appearances of some other...
> @whitequark what's next steps here? Apologies for the delay, let's just merge it. I'm a little uncertain if this is the right direction to go in, but if it...
Happy to merge if you squash the commits in the PR!
Take a look at this part: ``` reg \$auto$verilog_backend.cc:2352:dump_module$1 = 0; // ... always @* begin if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end // ... end ``` This is equivalent to: ```...
I see. I don't have access to Xcelium (and I've never used it) so I wouldn't really be able to help here.
Would be fixed by #1235.
Sorry, I really don't like analyzing probe-rs logs because when it can't find the chip it fills the log with megabytes of garbage.. try probe-rs matrix?