Catherine

This now has a merge conflict with `memory-25x`, could you rebase please?

Have you been able to look into the changes required?

> The generated Verilog file is pretty messy. > I have a ULX3S board and the generated Verilog file for the same Blinky example generates much cleaner code. > What...

These two files are not comparable. Your ULX3S Verilog file doesn't use an Amaranth platform, and if it did they'd look fairly similar. Amaranth extensively uses modules for code reuse....

In order for this PR to be complete and mergeable I expect the following items to be done: - [x] platform should output `.il` for toplevel - [x] platform should...

> * amaranth-boards should have a board file PR that can at least produce a working blinky for the platform, with the correct 1 Hz period I just realized that...

I have "GateMate FPGA Starter Kit" which is a blue board with a different layout than what you posted.

Sounds good to me. For now you testing on your own board is OK (managing review of two boards is a lot more difficult than one), I'll hack together a...

I have reviewed the [CologneChip Primitive Library](https://www.colognechip.com/docs/ug1001-gatemate1-primitives-library-latest.pdf) just now. In addition to the list above, the following primitives will need to be appropriately integrated into the platform: 1. I/O buffers:...

If you put the following contents into a file `.../cc-toolchain-linux/settings.sh`: ```bash export PATH=.../cc-toolchain-linux/bin/openFPGALoader:.../cc-toolchain-linux/bin/p_r:.../cc-toolchain-linux/bin/yosys:${PATH} ``` and then put `export AMARANTH_ENV_GATEMATE=.../cc-toolchain-linux/settings.sh` into your `~/.bashrc`, then you will be able to build Amaranth...