CPU: The AIB bit in MMU PDR register set independant of ACF field

[wfjm]

The MMU should set the AIB A bit in the the PDR only when "trap condition is met by the Access Control Field (ACF)". Thus for

   ACF=001 read-only  trap on read
   ACF=100 read/write trap on read or write
   ACF=101 read/write trap on write

The current pdp11_mmu implementation always sets the bit, the logic is simply

    if doabort = '0' then
      AIB_SETA <= '1';
      AIB_SETW <= CNTL.wacc or CNTL.macc;
    end if;

Since the MMU trap mechanism is is only available on 11/45 and 11/70, but not in the J11, it is not used by common operating systems.

Therefore this is considered a to be a minor deficit. Will be fixed in an upcoming release.

originally filed as issue w11a_V0.50-5 and TCK-029 dated 2009-05-09.