westerndigitalcorporation
Error parsing $var declaration where identifier contains square brackets
When parsing a $var directive that both contains a square bracket as part of the identifier AND a bit index declared afterwards, pyvcd will fail to process it properly and raise vcd.reader.VCDParseError: [lineno]:[col]: Expected $end. This can occur in VCDs generated for constructs like reg [31:0] regs [31:0] that are an array of vectors, where the resulting VCD would have the declaration $var wire 32 Q! regs[0] [31:0] $end (I had this occur in a file generated by Verilator).
I had difficulty finding the official IEEE Verilog standard's definition of what an "identifier" is, but it seems to me that in the above example, regs[0] would be considered part of the identifier, and [31:0] would be considered the bit index. If you (the maintainers) think this interpretation is correct, then I already have a fix + test case that does this, which I can file a PR for.
(screenshot of the relevant portion of the spec that I could find):
I have the same issue with definitions coming from a generate loop:
$scope module genblock[3].mod $end
will also raise the afore mentioned error.
Also I have this error, could you please share the fix meanwhile is officially fixed?
Currently I am just preprocessing the VCD with sed to make them readable by pyvcd.
sed -E 's/\[([[:digit:]]+)\]/_\1_/g' waves.vcd > waves2.vcd
sed -i -E 's/\$var ([^ ]+ [^ ]+ [^ ]+) (\\)/$var \1 _/g' waves2.vcd